This invention is directed towards an apparatus and method for controlling the running of a data processing unit, and more particularly to the bus cycle running time of a central processing unit such as a personal computer.
Significant advancements have been made to increase the operating speed of central processing units (CPU), dynamic access memories (DRAM) and erasable programmable read only memories (EPROM). The improved operating speeds of the CPU, DRAM and EPROM permit new products to be introduced into the marketplace each year having faster processing speeds. Improved processing speeds can be realized by increasing the clock pulse frequency of the CPU and by using high speed memories (e.g. DRAM or EPROM).
The operating speeds of existing input/output units (I/O) relative to CPUs and memory devices, however, have remained constant such that the operating speeds of CPUs and memory devices is now incompatible with the operating speeds of existing I/O devices. Conventional CPUs overcome this incompatibility by employing a wait step which slows down the bus cycle running time of the CPU. More particularly, a ready terminal of the CPU is held at a low logic level to create the wait step in the bus cycle running time of the CPU. Coordination between the high speed CPU and low speed I/O is achieved.
A conventional data processing unit 100 employing this wait step technique is illustrated in FIG. 15. For illustrative purposes only, data processing unit 100 has been simplified to include only those portions necessary to distinguish the same from the invention. Data processing apparatus 100 includes a CPU 21 such as an 80286, 8 MHz version manufactured by the Intel Company. CPU 21 includes a clock (CLK) input for receiving pulses of a clock (CLK) signal. The frequency of these pulses is about twice the operating speed of CPU 21. Three output terminals M/IO, S1 and SO of CPU 21 produce output signals M/IO, SI and SO, respectively.
Processing of data by CPU 21 requires a number of different bus cycles. These different bus cycles and the corresponding logic are represented by output signals M/IO, S1 and S0 as shown in FIG. 16. The different bus cycles during the running of CPU 21 can be extended when a READY terminal of CPU 21 is at a high logic level. When the signal provided to the READY terminal once again assumes a low logic level, as shown in FIG. 15, extension of the bus cycle ends. CPU 21 also includes address buses A23-A0 and a plurality of data buses D15-D0. A command decode circuit 2 in response to signals M/IO, S1 and SO produces a plurality of command signals IOR, IOW, MEMR and MEMW which correspond to different bus cycle conditions of FIG. 16. An oscillator 23 produces the pulses of signal CLK at a frequency of 16 MHz which is supplied to a CLK input of CPU 21 and a clock input of command decode circuit 2.
Output signals MEMR and MEMW of command decode circuit 2 for reading and writing from a memory 50, respectively, are supplied in combination with corresponding address signals traveling along address buses A23-A0 from CPU 1 to a memory controller 53. Data is written into or read from memory device 50 by CPU 1 based on memory address signals traveling along a plurality of buses 60 and memory control signals traveling along a plurality of buses 65 supplied from memory controller 53.
FIG. 17 illustrates the timing relationship between the signals produced by oscillator 13, CPU 21 and command decode circuit 2. CPU 21 includes a memory read bus cycle T31, an I/O read bus cycle T32, a memory write bus cycle T33 and a I/O write bus cycle T34. Each bus cycle includes two clock cycles TS and TC. Clock cycles TS and TC each include two pulses of the CLK signal. Each pulse of the CLK signal has a width of 62.5 ns. Accordingly, clock cycles TS and TC each have a cycle time of 125 ns and each bus cycle T31, T32, T33, T34 has a bus cycle time of 250 ns.
During clock cycle TS of each bus cycle, output signals M/IO, S1 and S0 are produced by CPU 21 to identify each of the bus cycles. Command decode circuit 2 decodes signals M/IO, S1 and S0. Thereafter, during clock cycle TC of bus cycles. T31, T32, T33 and T34 command signals MEMR, IOR, MEMW and IOW are produced by command decode circuit 2, respectively. The pulse length of each of these command signals is about 125 ns.
Output signals MEMR and MEMW of command d code circuit 2 for reading and writing from a memory 50, respectively, are supplied in combination with corresponding address signals traveling along address buses A23-A0 from CPU 1 to a memory controller 53. Data is written into or read from memory device 50 by CPU 1 based on memory address signals traveling along a plurality of buses 60 and memory control signals traveling along a plurality of buses 65 supplied from memory controller 53.
As shown in FIG. 18, a modified conventional data processing apparatus 120 permits the speed at which data is processed to be increased compared to unit 100. Unit 120 includes a CPU 1 (809286, 12 MHz version), a command decode circuit 12 and an oscillator 13 which operate in substantially the same manner as CPU 21, command decode circuit 2 and oscillator 23 of unit 100, respectively. Oscillator 13 produces a CLK signal having a 24 MHz frequency. Data processing apparatus 120 is otherwise substantially the same as unit 100 except that a READY control circuit 16 provides a READY signal to CPU 1 and command decode circuit 12 so that certain bus cycle times are extended.
As shown in FIG. 19, each clock cycle TS and TC has two clock pulses each of which has a time interval of about 41.7 ns. Accordingly, clock cycles TS and TC each have a time interval of about 82.3 ns. The time intervals of bus cycles T21, T22, T23 and T24 of unit 120 are each 167 ns. The time intervals of bus cycles T31, T32, T33 and T34, however, are each 250 ns. The reduction in bus cycle times, which is approximately 33%, is due to the increase in the frequency of CLK signal from 16 MHz to 24 MHz. Generally, read bus cycle T31 and memory write bus cycle T33 are compatible with high speed memory devices. Conventional I/O devices, however, cannot operate at a bus cycle time of 167 ns but rather require a bus cycle time of approximately 250 ns.
READY control circuit 16 provides a wait step to extend I/O read bus cycle T22 and I/O write bus cycle T24 to about 250 ns. The wait step is not employed during memory read bus cycle T21 and memory write bus cycle T23. Command signals IOR and IOW each include one wait step of approximately 83.3 ns. Since memory read bus cycle T21 and memory write bus cycle T23 do not require a wait step, each of these bus cycles has only one TC clock cycle. The time interval of cycles T21 and T23 are each about 167 ns. I/O read bus cycle T22 and I/O write bus cycle T24 each have one TS clock cycle and two TC clock cycles spanning a time interval of 250 ns. Command signals IOR and IOW are produced during the corresponding TC clock cycles of bus cycle T22 and T24, respectively. The additional TC clock cycle during bus cycles T22 and T24 is due to the READY signal being at a high logic level at the end of the first TC clock cycle of bus cycle T22 and T24.
Data processing apparatus 120 controls its running speed by controlling the READY signals applied to CPU 1. Desired bus cycles are extended based on the logic level of the READY signal. When the READY signal is at a high logic level, a wait step is added to the running time of the bus cycle. Accordingly, the bus cycle of CPU 1 can be made compatible with the slower operating speed of the I/O device.
The foregoing method for controlling the running speed of apparatus 120 to accommodate the slower operating speed of an I/O device has several drawbacks. More particularly, data processing units such as personal computers have become standardized. Use of a connector (i.e. option slot) to add an extended board having additional functions is commonly employed to upgrade the personal computer. Various kinds of extended boards are available from a variety of sources including special extended board manufacturers and personal computer manufacturers. The use of extended boards for personal computers is steadily increasing in importance. New products offered by personal computer manufacturers must be compatible with existing extended boards (i.e. used with older generations of personal computers).
For exemplary purposes only, assume data processing apparatus 120 represents a new product to be used with I/O devices designed for use with data processing unit 100. The IOR and IOW command signals required by the I/O devices are produced during the TC clock cycles of bus cycles T32 and T34 of FIG. 17, respectively. CPU 1, however, produces command signals IOR and IOW during clock cycles TC of bus cycles T22 and T24 of FIG. 19. Bus cycles T22 and T24 include a wait step whereas clock cycles T32 and T34 have no wait step. The pulse lengths of command signals IOW and IOR are each 125 ns for bus cycles T32 and T34, respectively. The pulse lengths of command signals IOW and IOR are each 167 ns for bus cycles T22 and T24, respectively. The I/O write data command signals between the I/O devices and CPU 1 also differ in setting up and holding times. The differences in pulse length, setting up and holding times prevent some extended boards for new products from being used with I/O devices.
The addition of a wait step to accommodate the slower operational speed of an I/O device also creates a far less efficient use of CPU 1. More particularly, since the CLK signal produced by oscillator 13 of unit 120 has a frequency of 24 MHz, bus cycle times increase in steps of 83.3 ns for each wait step (i.e. 166.7 ns for a 0-wait step, 250 ns for a 1-wait step, 333.3 ns for a 2-wait step, etc.). CPU 1 is operable for providing access to a DRAM having a cycle time of 180 ns commonly referred to as a DRAM for speed of 100 ns (i.e. the row access strobe (RAS) access time). RAS is an input terminal of a DRAM. Such access by CPU 1 can be supplied on a stable basis. The bus cycle of CPU 1 without a wait step is 166.7 ns which is less than the cycle time of 180 ns required by the DRAM. Access to the DRAM cannot be provided without a wait step. Conventional data processing apparatuses such as apparatus 120 provide the wait step to ensure access to the DRAM. The bus cycle time with one wait step, however, is 250 ns which is far greater than the 180 ns time interval required for access to the DRAM. CPU 1 operates on an inefficient basis, that is, about 70 ns of the 250 ns bus cycle time are not used by CPU 1. In particular, optimum performance of CPU 1 is not realized due to the frequency of the CLK signal being preset.
Data processing apparatuses are also designed to operate within a temperature range of between about 0.degree. C. through 40.degree. C. The corresponding voltage range (V.sub.cc) is about 4.75 volts through 5.25 volts. At a temperature of 40.degree. C. and line voltage of 4.75 volts, the CPU can operate at a clock frequency of 9 MHz. At a temperature of 25.degree. C. and line voltage of 5.0 volts, the CPU can operate at a clock frequency of 10 MHz. At a temperature of 0.degree. C. and line voltage of 5.25 volts, the CPU can operate at a clock frequency of 11 MHz. Data processing apparatus 120, however, is preset at 9 MHz and operates at about 25.degree. C. at a line voltage of 5.0 volts even though oscillator 120 is designed to operate at a clock frequency of 10 MHz. Consequently, the operating speed of data processing unit 120 is less than optimum. When the CLK signal is 10 MHz, data processing unit 120 normally cannot operate at a temperature of 40.degree. C. and line voltage of 4.75 volts.
Accordingly, it is desirable to provide a data processing apparatus in which the running speed of the CPU can be adjusted based on the type of bus cycle to more efficiently utilize the CPU. The frequency of the clock signal should dynamically reduce the bus cycle time to increase the processing speed of the CPU when using high speed memory devices and to increase the bus cycle time to decrease the processing speed of the CPU when communicating with I/O devices. Variation of the clock signal frequency should also be provided based on the ambient temperature conditions and line voltage to optimize the efficiency of the data processing unit.